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Translacja projektu (UART-Tx) z Verilog'u do VHDL

Autor Wiadomość
FlyingDutch 




Posty: 287
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Otrzymał 17 piw(a)
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Programuję w:
C++,Python
Wysłany: 14-01-2018, 11:13   Translacja projektu (UART-Tx) z Verilog'u do VHDL

Cześć,

jako, że większość kodu, który piszę w swoich projektach FPGA to VHDL, postanowiłem "przetłumaczyć" projekt UART (który opisywałem w innych postach z tego działu) z Verilog'a na VHDL. Ponieważ moja znajomość Verilog'a jest na bardzo niskim poziomie stanowi to dla mnie spory problem. Posiłkowałem się przy tym zadaniu kompilatorem "Icarus Verilog" (opisanym w jednym z postów). Automatycznie wygenerowany kod z Icarusa następnie modyfikowałem ręcznie, ponieważ w wielu miejscach kod był bardzo nieefektywny (bardzo dziwne konwersje typów itp.).

Aktualnie mam przetłumaczony cały projekt UART. Teoretycznie kod się syntetyzuje (nie ma błędów syntezy), ale w praktyce nie tworzy nic w strukturze FPGA. Nie mogę też obejrzeć podglądu RTL wygenerowanego układu. Mam mnóstwo warning'ów świadczących o tym, że według środowiska ISE, poszczególne moduły składowe nie zostały (w modułach wyższego rzędu podłączone prawidłowo).

Pierwotny projekt zawierał dużo Verilog'owych params pozamieniałem je na generics w VHDL. Poza tym includowany w Verilog'u plik ze stałymi definiującymi prędkości transmisji zamieniłem na package VHDL'a, który potem używam w innych entity projektu.

A tak wygląda raport po syntezie układu (VHDL):



Jak widać w sekcji "Device Utilization Sumarry" układ po syntezie zajmuje 3 porty I/O i zero LUTs !

Poniżej raport z syntezy układu (konsola):
Kod programu: Zaznacz cały


Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "C:/Users/mgabr/Spartan3/UART_SEND_VHDL/txstr.xst" -ofn "C:/Users/mgabr/Spartan3/UART_SEND_VHDL/txstr.syr"
Reading design: txstr.prj

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Users/mgabr/Spartan3/UART_SEND_VHDL/baudrates.vhd" in Library work.
Package <baudrates> compiled.
Package body <baudrates> compiled.
Compiling vhdl file "C:/Users/mgabr/Spartan3/UART_SEND_VHDL/baudgen_tx.vhd" in Library work.
Entity <baudgen_tx> compiled.
Entity <baudgen_tx> (Architecture <from_verilog>) compiled.
Compiling vhdl file "C:/Users/mgabr/Spartan3/UART_SEND_VHDL/uart_tx.vhd" in Library work.
Entity <uart_tx> compiled.
Entity <uart_tx> (Architecture <from_verilog>) compiled.
Compiling vhdl file "C:/Users/mgabr/Spartan3/UART_SEND_VHDL/txstr.vhd" in Library work.
Entity <txstr> compiled.
WARNING:HDLParsers:817 - "C:/Users/mgabr/Spartan3/UART_SEND_VHDL/txstr.vhd" Line 161. Choice INI is not a locally static expression.
WARNING:HDLParsers:817 - "C:/Users/mgabr/Spartan3/UART_SEND_VHDL/txstr.vhd" Line 164. Choice TXCAR is not a locally static expression.
WARNING:HDLParsers:817 - "C:/Users/mgabr/Spartan3/UART_SEND_VHDL/txstr.vhd" Line 168. Choice NEXTCAR is not a locally static expression.
Entity <txstr> (Architecture <from_verilog>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <txstr> in library <work> (architecture <from_verilog>) with generics.
    BAUDRATE = 1250
    INI = "00"
    NEXTCAR = "10"
    STOP = "11"
    TXCAR = "01"

Analyzing hierarchy for entity <uart_tx> in library <work> (architecture <from_verilog>) with generics.
    BAUDRATE = 1250
    N = 17

Analyzing hierarchy for entity <baudgen_tx> in library <work> (architecture <from_verilog>) with generics.
    BAUDRATE = 1250
    N = 17


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing generic Entity <txstr> in library <work> (Architecture <from_verilog>).
    BAUDRATE = 1250
    INI = "00"
    NEXTCAR = "10"
    STOP = "11"
    TXCAR = "01"
INFO:Xst:2679 - Register <char_count> in unit <txstr> has a constant value of 000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <data<0>> in unit <txstr> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <data<1>> in unit <txstr> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <data<2>> in unit <txstr> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <data<3>> in unit <txstr> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <data<4>> in unit <txstr> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <data<5>> in unit <txstr> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <data<6>> in unit <txstr> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <data<7>> in unit <txstr> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <state> in unit <txstr> has a constant value of 00 during circuit operation. The register is replaced by logic.
Entity <txstr> analyzed. Unit <txstr> generated.

Analyzing generic Entity <uart_tx> in library <work> (Architecture <from_verilog>).
    BAUDRATE = 1250
    N = 17
Entity <uart_tx> analyzed. Unit <uart_tx> generated.

Analyzing generic Entity <baudgen_tx> in library <work> (Architecture <from_verilog>).
    BAUDRATE = 1250
    N = 17
Entity <baudgen_tx> analyzed. Unit <baudgen_tx> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <baudgen_tx>.
    Related source file is "C:/Users/mgabr/Spartan3/UART_SEND_VHDL/baudgen_tx.vhd".
    Found 1-bit register for signal <divcounter>.
    Summary:
    inferred   1 D-type flip-flop(s).
Unit <baudgen_tx> synthesized.


Synthesizing Unit <uart_tx>.
    Related source file is "C:/Users/mgabr/Spartan3/UART_SEND_VHDL/uart_tx.vhd".
    Using one-hot encoding for signal <state>.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <state> of Case statement line 184 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
       - add an 'INIT' attribute on signal <state> (optimization is then done without any risk)
       - use the attribute 'signal_encoding user' to avoid onehot optimization
       - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Using one-hot encoding for signal <bitc>.
    Found 2-bit register for signal <bitc>.
    Found 8-bit register for signal <data_r>.
    Found 10-bit register for signal <shifter>.
    Found 3-bit register for signal <state>.
    Found 1-bit register for signal <tx_Reg>.
    Summary:
    inferred  24 D-type flip-flop(s).
Unit <uart_tx> synthesized.


Synthesizing Unit <txstr>.
    Related source file is "C:/Users/mgabr/Spartan3/UART_SEND_VHDL/txstr.vhd".
WARNING:Xst:646 - Signal <ready> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <next_state> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <char_count> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cena> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <txstr> synthesized.

WARNING:Xst:524 - All outputs of the instance <BAUD0> of the block <baudgen_tx> are unconnected in block <uart_tx>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 4
 1-bit register                                        : 1
 10-bit register                                       : 1
 2-bit register                                        : 1
 3-bit register                                        : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:1710 - FF/Latch <shifter_0> (without init value) has a constant value of 1 in block <TX0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tx_Reg> (without init value) has a constant value of 1 in block <TX0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <shifter_1> of sequential type is unconnected in block <TX0>.
WARNING:Xst:2677 - Node <shifter_2> of sequential type is unconnected in block <TX0>.
WARNING:Xst:2677 - Node <shifter_3> of sequential type is unconnected in block <TX0>.
WARNING:Xst:2677 - Node <shifter_4> of sequential type is unconnected in block <TX0>.
WARNING:Xst:2677 - Node <shifter_5> of sequential type is unconnected in block <TX0>.
WARNING:Xst:2677 - Node <shifter_6> of sequential type is unconnected in block <TX0>.
WARNING:Xst:2677 - Node <shifter_7> of sequential type is unconnected in block <TX0>.
WARNING:Xst:2677 - Node <shifter_8> of sequential type is unconnected in block <TX0>.
WARNING:Xst:2677 - Node <shifter_9> of sequential type is unconnected in block <TX0>.
WARNING:Xst:2677 - Node <state_1> of sequential type is unconnected in block <uart_tx>.
WARNING:Xst:2677 - Node <state_2> of sequential type is unconnected in block <uart_tx>.
WARNING:Xst:2677 - Node <shifter_1> of sequential type is unconnected in block <uart_tx>.
WARNING:Xst:2677 - Node <shifter_2> of sequential type is unconnected in block <uart_tx>.
WARNING:Xst:2677 - Node <shifter_3> of sequential type is unconnected in block <uart_tx>.
WARNING:Xst:2677 - Node <shifter_4> of sequential type is unconnected in block <uart_tx>.
WARNING:Xst:2677 - Node <shifter_5> of sequential type is unconnected in block <uart_tx>.
WARNING:Xst:2677 - Node <shifter_6> of sequential type is unconnected in block <uart_tx>.
WARNING:Xst:2677 - Node <shifter_7> of sequential type is unconnected in block <uart_tx>.
WARNING:Xst:2677 - Node <shifter_8> of sequential type is unconnected in block <uart_tx>.
WARNING:Xst:2677 - Node <shifter_9> of sequential type is unconnected in block <uart_tx>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 3
 Flip-Flops                                            : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <divcounter> (without init value) has a constant value of 1 in block <baudgen_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <state_0> has a constant value of 1 in block <uart_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <shifter_0> (without init value) has a constant value of 1 in block <uart_tx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tx_Reg> (without init value) has a constant value of 1 in block <uart_tx>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <txstr> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block txstr, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

=========================================================================

Process "Synthesize - XST" completed successfully

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc txtstr_UCF.ucf -p xc3s50a-tq144-5 txstr.ngc txstr.ngd

Command Line: E:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -uc txtstr_UCF.ucf -p xc3s50a-tq144-5
txstr.ngc txstr.ngd

Reading NGO file "C:/Users/mgabr/Spartan3/UART_SEND_VHDL/txstr.ngc" ...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "txtstr_UCF.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...

Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "txstr.ngd" ...
Total REAL time to NGDBUILD completion:  5 sec
Total CPU time to NGDBUILD completion:   5 sec

Writing NGDBUILD log file "txstr.bld"...

NGDBUILD done.

Process "Translate" completed successfully

Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc3s50a-tq144-5 -cm area -detail -ir off -pr off -c 100 -o txstr_map.ncd txstr.ngd txstr.pcf
Using target part "3s50atq144-5".
Mapping design into LUTs...
WARNING:MapLib:23 - Short on signal rstn detected.
WARNING:MapLib:23 - Short on signal rstn detected.
WARNING:MapLib:23 - Short on signal rstn detected.
WARNING:MapLib:23 - Short on signal rstn detected.
WARNING:MapLib:23 - Short on signal rstn detected.
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
WARNING:PhysDesignRules:367 - The signal <clk_IBUF> is incomplete. The signal
   does not drive any load pins in the design.

Design Summary:
Number of errors:      0
Number of warnings:    6
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:       0 out of       0   0%
    Number of Slices containing unrelated logic:          0 out of       0   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Number of bonded IOBs:                  3 out of     108    2%

Average Fanout of Non-Clock Nets:                0.00

Peak Memory Usage:  275 MB
Total REAL time to MAP completion:  1 secs
Total CPU time to MAP completion:   1 secs

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "txstr_map.mrp" for details.

Process "Map" completed successfully

Started : "Place & Route".
Running par...
Command Line: par -w -intstyle ise -ol high -t 1 txstr_map.ncd txstr.ncd txstr.pcf



Constraints file: txstr.pcf.
Loading device for application Rf_Device from file '3s50a.nph' in environment E:\Xilinx\14.7\ISE_DS\ISE\.
   "txstr" is an NCD, version 3.2, device xc3s50a, package tq144, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.42 2013-10-13".


Design Summary Report:

 Number of External IOBs                           3 out of 108     2%

   Number of External Input IOBs                  1

      Number of External Input IBUFs              1
        Number of LOCed External Input IBUFs      1 out of 1     100%


   Number of External Output IOBs                 2

      Number of External Output IOBs              2
        Number of LOCed External Output IOBs      2 out of 2     100%


   Number of External Bidir IOBs                  0




Overall effort level (-ol):   High
Placer effort level (-pl):    High
Placer cost table entry (-t): 1
Router effort level (-rl):    High

Starting initial Timing Analysis.  REAL time: 1 secs
Finished initial Timing Analysis.  REAL time: 1 secs

WARNING:Par:288 - The signal clk_IBUF has no load.  PAR will not attempt to route this signal.

Starting Placer
Total REAL time at the beginning of Placer: 1 secs
Total CPU  time at the beginning of Placer: 1 secs

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:3f2606) REAL time: 1 secs

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:3f2606) REAL time: 1 secs

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:3f2606) REAL time: 1 secs

Phase 4.2  Initial Clock and IO Placement
Phase 4.2  Initial Clock and IO Placement (Checksum:3f2606) REAL time: 1 secs

Phase 5.30  Global Clock Region Assignment
Phase 5.30  Global Clock Region Assignment (Checksum:3f2606) REAL time: 1 secs

Phase 6.36  Local Placement Optimization
Phase 6.36  Local Placement Optimization (Checksum:3f2606) REAL time: 1 secs

Phase 7.8  Global Placement
Phase 7.8  Global Placement (Checksum:3f2606) REAL time: 1 secs

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:3f2606) REAL time: 1 secs

Phase 9.18  Placement Optimization
Phase 9.18  Placement Optimization (Checksum:3f2606) REAL time: 1 secs

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:3f2606) REAL time: 1 secs

Total REAL time to Placer completion: 1 secs
Total CPU  time to Placer completion: 1 secs
Writing design to file txstr.ncd



Starting Router


Phase  1  : 2 unrouted;      REAL time: 2 secs

Phase  2  : 2 unrouted;      REAL time: 2 secs

Phase  3  : 0 unrouted;      REAL time: 2 secs

Phase  4  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 secs

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 secs

Updating file: txstr.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 secs

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 secs

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 secs

Total REAL time to Router completion: 2 secs
Total CPU time to Router completion: 2 secs

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Number of Timing Constraints that were not applied: 1

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  NET "clk_IBUF" PERIOD = 83.3333333 ns HIG | N/A         |         N/A|         N/A|     N/A|         N/A
  H 50%                                     |             |            |            |        |           
----------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
   constraint is not analyzed due to the following: No paths covered by this
   constraint; Other constraints intersect with this constraint; or This
   constraint was disabled by a Path Tracing Control. Please run the Timespec
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 2 secs
Total CPU time to PAR completion: 2 secs

Peak Memory Usage:  278 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 3
Number of info messages: 0

Writing design to file txstr.ncd



PAR done!

Process "Place & Route" completed successfully

Started : "Generate Post-Place & Route Static Timing".
Running trce...
Command Line: trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml txstr.twx txstr.ncd -o txstr.twr txstr.pcf -ucf txtstr_UCF.ucf
Loading device for application Rf_Device from file '3s50a.nph' in environment
E:\Xilinx\14.7\ISE_DS\ISE\.
   "txstr" is an NCD, version 3.2, device xc3s50a, package tq144, speed -5

Analysis completed Sun Jan 14 09:54:56 2018
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 1 secs

Process "Generate Post-Place & Route Static Timing" completed successfully



Wklejam po kolei (od dołu hierarchii projektu) pliki oryginalne w Verilogu i ich przetłumaczone wersje VHDL:

1) baudgen.vh -> baudrates.vhd:
Kod programu: Zaznacz cały

//-----------------------------------------------------------------------------
//-- Constants for the serial asinchronous communication modules
//------------------------------------------------------------------------------
//-- (C) BQ. December 2015. Written by Juan Gonzalez (Obijuan)
//------------------------------------------------------------------------------
// These constans have been calculated for the ICESTICK board which have
// a 12MHz clock
//
//-- The calculation for the icestick board is:
//-- Divisor = 12000000 / BAUDRATE  (and the result is rounded to an integer number)
//--------------------------------------------------------------------------------
//-- The python3 script: baudgen.py contains the function for generating this table
//-----------------------------------------------------------------------------------

//-- Constants for obtaining standard BAURATES:
`define B115200 104
`define B57600  208
`define B38400  313

`define B19200  625
`define B9600   1250
`define B4800   2500
`define B2400   5000
`define B1200   10000
`define B600    20000
`define B300    40000


Kod programu: Zaznacz cały

--
--    Package File Template
--
--    Purpose: This package defines supplemental types, subtypes,
--        constants, and functions
--
--   To use any of the example code shown below, uncomment the lines and modify as necessary
--

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package baudrates is

   -- Definition of constants
   constant B115200 : natural := 104;
    constant B57600  : natural := 208;
   constant B38400  : natural := 313;
   constant B19200  : natural := 625;
    constant B9600   : natural := 1250;
    constant B4800   : natural := 2500;
    constant B2400   : natural := 5000;
    constant B1200   : natural := 10000;
    constant B600    : natural := 20000;
    constant B300    : natural := 40000;
 
end baudrates;

package body baudrates is
 
end baudrates;


2) baudgen_tx.v -> baudgen_tx.vhd

Kod programu: Zaznacz cały

//-----------------------------------------------------------------------------
//-- Baudrate generator
//-- It generates a square signal, with a frequency for communicating at the given
//-- given baudrate
//-- The output is set to 1 only during one clock cycle. The rest of the time is 0
//--------------------------------------------------------------------------------
//-- (c) BQ. December 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"

//----------------------------------------------------------------------------------------
//-- baudgen module
//--
//-- INPUTS:
//--     -clk: System clock (12 MHZ in the iceStick board)
//--     -clk_ena: clock enable:
//--            1. Normal working: The squeare signal is generated
//--            0: stoped. Output always 0
//-- OUTPUTS:
//--     - clk_out: Output signal. Pulse width: 1 clock cycle. Output not registered
//--                It tells the uart_tx when to transmit the next bit
//--      __                                                         __
//--   __| |________________________________________________________| |________________
//--   ->  <- 1 clock cycle
//--
//---------------------------------------------------------------------------------------
module baudgen_tx #(
          parameter BAUDRATE = `B9600  //-- Default baudrate
)(
          input wire rstn,              //-- Reset (active low)
          input wire clk,               //-- System clock
          input wire clk_ena,           //-- Clock enable
          output wire clk_out           //-- Bitrate Clock output
);

//-- Number of bits needed for storing the baudrate divisor
//localparam N = $clog2(BAUDRATE);
localparam N = 17;

//-- Counter for implementing the divisor (it is a BAUDRATE module counter)
//-- (when BAUDRATE is reached, it start again from 0)
reg [N-1:0] divcounter = 0;

always @(posedge clk)

  if (!rstn)
    divcounter <= 0;

  else if (clk_ena)
    //-- Normal working: counting. When the maximum count is reached, it starts from 0
    divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
  else
    //-- Counter fixed to its maximum value
    //-- When it is resumed it start from 0
    divcounter <= BAUDRATE - 1;

//-- The output is 1 when the counter is 0, if clk_ena is active
//-- It is 1 only for one system clock cycle
assign clk_out = (divcounter == 0) ? clk_ena : 0;


endmodule


Kod programu: Zaznacz cały

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    10:04:05 01/11/2018
-- Design Name:
-- Module Name:    baudgen_tx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use Work.baudrates.all;

entity baudgen_tx is
  generic ( BAUDRATE : natural := B9600; -- BAUDRATE = 9600
            N        : integer := 17 -- Number of bits needed for storing the baudrate divisor = $clog2(BAUDRATE)
  );
   port (
    clk : in std_logic;
    clk_ena : in std_logic;
    clk_out : out std_logic;
    rstn : in std_logic
  );
end entity;

architecture from_verilog of baudgen_tx is
    signal divcounter : STD_LOGIC_VECTOR(N-1 downto 0);
   
begin
 
  process (clk) is
  begin
    if rising_edge(clk) then
      if (not rstn) = '1' then
        divcounter <=  (others => '0');
      else
        if clk_ena = '1' then
              -- divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
             if (divcounter = std_logic_vector(to_unsigned(BAUDRATE - 1, divcounter'length))) then
              divcounter <= (others => '0');
           else
             divcounter <= std_logic_vector(unsigned(divcounter) + 1 );
           end if;   
        else
            --divcounter <= BAUDRATE - 1;
          divcounter <= std_logic_vector(to_unsigned(BAUDRATE - 1, divcounter'length));
        end if;
      end if;
    end if;
  end process;
 
  --assign clk_out = (divcounter == 0) ? clk_ena : 0;
  clk_out <= clk_ena when (divcounter = std_logic_vector(to_unsigned(0, divcounter'length))) else '0';
   
end architecture;


3) uart_tx.v -> uart_tx.vhd:

Kod programu: Zaznacz cały

//----------------------------------------------------------------------------
//-- Asynchronous serial transmitter Unit
//------------------------------------------
//-- (C) BQ. December 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Tested at all the standard baudrates:
//-- 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200
//----------------------------------------------------------------------------
//-- Although this transmitter has been written from the scratch, it has been
//-- inspired by the one developed in the swapforth proyect by James Bowman
//--
//-- https://github.com/jamesbowman/swapforth
//--
//----------------------------------------------------------------------------
`default_nettype none

`include "baudgen.vh"

//--- Serial transmitter unit module
//--- TX output is not registered
module uart_tx #(
         parameter BAUDRATE = `B9600  //-- Default baudrate
)(
         input wire clk,        //-- System clcok (12MHz in the ICEstick)
         input wire rstn,       //-- Reset  (Active low)
         input wire start,      //-- Set to 1 for starting the transmission
         input wire [7:0] data, //-- Byte to transmit
         output reg tx,         //-- Serial data output
         output reg ready      //-- Transmitter ready (1) / busy (0)
);


//-- Transmission clock
wire clk_baud;

//-- Bitcounter
reg [3:0] bitc;

//-- Registered data
reg [7:0] data_r;

//--------- control signals
reg load;    //-- Load the shifter register / reset
reg baud_en; //-- Enable the baud generator

//-- fsm states
localparam IDLE  = 0;  //-- Idle state
localparam START = 1;  //-- Start transmission
localparam TRANS = 2;  //-- Transmitting data

//-- Registers for storing the states
reg [1:0] state;
reg [1:0] next_state;


//-------------------------------------
//-- DATAPATH
//-------------------------------------

//-- Register the input data
always @(posedge clk)
  if (start == 1 && state == IDLE)
    data_r <= data;

//-- 1 bit start + 8 bits datos + 1 bit stop
//-- Shifter register. It stored the frame to transmit:
//-- 1 start bit + 8 data bits + 1 stop bit
reg [9:0] shifter;

//-- When the control signal load is 1, the frame is loaded
//-- when load = 0, the frame is shifted right to send 1 bit,
//--   at the baudrate determined by clk_baud
//--  1s are introduced by the left
always @(posedge clk)
  //-- Reset
  if (rstn == 0)
    shifter <= 10'b11_1111_1111;

  //-- Load mode
  else if (load == 1)
    shifter <= {data_r,2'b01};

  //-- Shift mode
  else if (load == 0 && clk_baud == 1)
    shifter <= {1'b1, shifter[9:1]};

//-- Sent bit counter
//-- When load (=1) the counter is reset
//-- When load = 0, the sent bits are counted (with the raising edge of clk_baud)
always @(posedge clk)
  if (!rstn)
    bitc <= 0;

  else if (load == 1)
    bitc <= 0;
  else if (load == 0 && clk_baud == 1)
    bitc <= bitc + 1;

//-- The less significant bit is transmited through tx
//-- It is a registed output, because tx is connected to an Asynchronous bus
//--  and the glitches should be avoided
always @(posedge clk)
  tx <= shifter[0];

//-- Baud generator
baudgen_tx #( .BAUDRATE(BAUDRATE))
BAUD0 (
    .rstn(rstn),
    .clk(clk),
    .clk_ena(baud_en),
    .clk_out(clk_baud)
  );

//------------------------------
//-- CONTROLLER
//------------------------------


//-- Transition between states
always @(posedge clk)
  if (!rstn)
    state <= IDLE;
  else
    state <= next_state;

//-- Control signal generation and next states
always @(*) begin

  //-- Default values
  next_state = state;      //-- Stay in the same state by default
  load = 0;
  baud_en = 0;

  case (state)

    //-- Idle state
    //-- Remain in this state until start is 1
    IDLE: begin
      ready = 1;
      if (start == 1)
        next_state = START;
    end

    //-- 1 cycle long
    //-- turn on the baudrate generator and the load the shift register
    START: begin
      load = 1;
      baud_en = 1;
      ready = 0;
      next_state = TRANS;
    end

    //-- Stay here until all the bits have been sent
    TRANS: begin
      baud_en = 1;
      ready = 0;
      if (bitc == 11)
        next_state = IDLE;
    end

    default:
      ready = 0;

  endcase
end

endmodule



Kod programu: Zaznacz cały

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    09:53:41 01/11/2018
-- Design Name:
-- Module Name:    uart_tx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use Work.baudrates.all;

--- Serial transmitter unit module
--- TX output is not registered
entity uart_tx is
  generic ( BAUDRATE : natural := B9600; -- BAUDRATE = 9600
            N        : integer := 17 -- Number of bits needed for storing the baudrate divisor = $clog2(BAUDRATE)
  );
  port (
    clk : in std_logic;
    data : in unsigned(7 downto 0);
    ready : out std_logic;
    rstn : in std_logic;
    start : in std_logic;
    tx : out std_logic
  );
end entity;

architecture from_verilog of uart_tx is

  component baudgen_tx is
    generic ( BAUDRATE : natural := B9600; -- BAUDRATE = 9600
            N        : integer := 17 -- Number of bits needed for storing the baudrate divisor = $clog2(BAUDRATE)
    );
    port (
      clk : in std_logic;
      clk_ena : in std_logic;
      clk_out : out std_logic;
      rstn : in std_logic
    );
  end component;

-- Transmission clock
signal clk_baud : std_logic;
-- Bitcounter
signal bitc : unsigned(3 downto 0);  -- Declared at uart_tx.v:38
-- Registered data
signal data_r : unsigned(7 downto 0);  -- Declared at uart_tx.v:41
--------- control signals
signal load : std_logic;  -- Load the shifter register / reset
signal baud_en : std_logic; -- Enable the baud generator

-- localparam IDLE  = 0;  //-- Idle state
-- localparam START = 1;  //-- Start transmission
-- localparam TRANS = 2;  //-- Transmitting data

-- fsm states - original
--signal IDLE : integer range 0 to 2 := 0; -- Idle state
--signal START : integer range 0 to 2 := 1; -- Start transmission
--signal TRANS : integer range 0 to 2 := 2; -- Transmitting data

-- Registers for storing the states
type STATE_T is (IDLE, STARTS, TRANS);
signal state, next_state: STATE_T;

signal ready_Reg : std_logic ;
signal tx_Reg : std_logic ;

-- 1 bit start + 8 bits datos + 1 bit stop
-- Shifter register. It stored the frame to transmit:
-- 1 start bit + 8 data bits + 1 stop bit
 signal shifter : unsigned(9 downto 0);  -- Declared at uart_tx.v:69
--signal shifter : std_logic_vector(9 downto 0) := (others=>'0');
 
begin
  ready <= ready_Reg;
  tx <= tx_Reg;
 
  -- Generated from instantiation at uart_tx.v:108
  BAUD0: baudgen_tx
    port map (
      clk => clk,
      clk_ena => baud_en,
      clk_out => clk_baud,
      rstn => rstn
    );
 
  -- Register the input data
  process (clk) is
  begin
    if rising_edge(clk) then
      if (start = '1' and state = IDLE) then
        data_r <= data;
      end if;
    end if;
  end process;
 
  -- When the control signal load is 1, the frame is loaded
  -- when load = 0, the frame is shifted right to send 1 bit,
  --   at the baudrate determined by clk_baud
  --  1s are introduced by the left
  process (clk) is
  begin
    if rising_edge(clk) then
      if (rstn = '0') then
        shifter <= "1111111111";
      else
        if (load = '1') then
          shifter <= data_r & "01";
        else
          if (load = '0' and clk_baud = '1') then
            shifter <= '1' & shifter(1 + 8 downto 1);
          end if;
        end if;
      end if;
    end if;
  end process;
   
  -- Sent bit counter
  -- When load (=1) the counter is reset
  -- When load = 0, the sent bits are counted (with the raising edge of clk_baud)
  process (clk) is
  begin
    if rising_edge(clk) then
      if (not rstn) = '1' then
        bitc <= X"0";
      else
        if (load = '1') then
          bitc <= X"0";
        else
          if (load = '0' and clk_baud = '1') then
            bitc <= bitc + X"1";
          end if;
        end if;
      end if;
    end if;
  end process;
 
  -- Generated from always process in uart_tx (uart_tx.v:103)
  process (clk) is
  begin
    if rising_edge(clk) then
      tx_Reg <= shifter(0);
    end if;
  end process;
     
  ------------------------------
  -- CONTROLLER
  ------------------------------
 
  -- Transition between states
  process (clk) is
  begin
    if rising_edge(clk) then
      if (not rstn) = '1' then
        state <= IDLE;
      else
        state <= next_state;
      end if;
    end if;
  end process;
 
  -- Generated from always process in uart_tx (uart_tx.v:128)
  -- Control signal generation and next states
  process (state, start, bitc) is
  begin
    -- Default values
    next_state <= state; -- Stay in the same state by default
    load <= '0';
    baud_en <= '0';

    case state is
       -- Idle state
      -- Remain in this state until start is 1
      when IDLE =>
        ready_Reg <= '1';
        if (start = '1') then
          next_state <= STARTS;
        end if;
        -- 1 cycle long
      -- turn on the baudrate generator and the load the shift register
      when STARTS =>
        load <= '1';
        baud_en <= '1';
        ready_Reg <= '0';
        next_state <= TRANS;
        -- Stay here until all the bits have been sent
      when TRANS =>
        baud_en <= '1';
        ready_Reg <= '0';
        if (bitc = "11") then
          next_state <= IDLE;
        end if;
      when others =>
        ready_Reg <= '0';
    end case;
  end process;
 
end architecture;



4) txtstr.v -> txtstr.vhd:

Kod programu: Zaznacz cały

//-----------------------------------------------------------------------------------------
//-- txstr: Uart_tx example 2
//-- Transmission of string
//-- The reset signal is connected to the dtr signal (in file txstr.pcf)
//-- Fot this example to work is necessary to open a serial terminal (gtkterm for example)
//-- and deactivate DTR. Every time a reset is done, a string appears on the terminal
//-- Fixed BAUDRATE: 115200
//-----------------------------------------------------------------------------------------
//-- (C) BQ. December 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//-----------------------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"

//-- Top entity
module txstr #(
          parameter BAUDRATE = `B9600
)(
          input wire clk,   //-- System clock
          input wire rstn,  //-- Reset (active low)
          output wire tx    //-- Serial data output
);

//-- Connecting wires
wire ready;
reg start = 0;
reg [7:0] data;

//-- Serial Unit instantation
uart_tx #(
    .BAUDRATE(BAUDRATE)  //-- Set the baudrate

  ) TX0 (
    .clk(clk),
    .rstn(rstn),
    .data(data),
    .start(start),
    .tx(tx),
    .ready(ready)
);
//-- It only counts when the cena control signal is enabled
reg [2:0] char_count;
reg cena; 

//-- Multiplexer with the 8-character string to transmit
always @*
  case (char_count)
    8'd0: data <= "H";
    8'd1: data <= "e";
    8'd2: data <= "l";
    8'd3: data <= "l";
    8'd4: data <= "o";
    8'd5: data <= "!";
    8'd6: data <= ".";
    8'd7: data <= ".";
    default: data <= ".";
  endcase

//-- Characters counter
              //-- Counter enable

always @(posedge clk)
  if (!rstn)
    char_count = 0;
  else if (cena)
    char_count = char_count + 1;


//--------------------- CONTROLLER

localparam INI = 0;
localparam TXCAR = 1;
localparam NEXTCAR = 2;
localparam STOP = 3;

//-- fsm state
reg [1:0] state;
reg [1:0] next_state;

//-- Transition between states
always @(posedge clk) begin
  if (!rstn)
    state <= INI;
  else
    state <= next_state;
end

//-- Control signal generation and next states
always @(*) begin
  next_state = state;
  start = 0;
  cena = 0;

  case (state)
    //-- Initial state. Start the trasmission
    INI: begin
      start = 1;
      next_state = TXCAR;
    end

    //-- Wait until one car is transmitted
    TXCAR: begin
      if (ready)
        next_state = NEXTCAR;
    end

    //-- Increment the character counter
    //-- Finish when it is the last character
    NEXTCAR: begin
      cena = 1;
      if (char_count == 7)
        next_state = STOP; //next_state = STOP; | next_state = INI;
      else
        next_state = INI;
    end

  endcase
end


endmodule


Kod programu: Zaznacz cały

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    10:06:46 01/11/2018
-- Design Name:
-- Module Name:    txstr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use Work.baudrates.all;


-- Top entity
-- Generated from Verilog module txstr (txstr.v:16)
--   BAUDRATE = 104
--   INI = 0
--   NEXTCAR = 2
--   STOP = 3
--   TXCAR = 1
entity txstr is
  generic ( BAUDRATE : natural := B9600; -- BAUDRATE = 9600
                INI      : unsigned (1 downto 0) := "00";
                TXCAR    : unsigned (1 downto 0) := "01";
                NEXTCAR  : unsigned (1 downto 0) := "10";
                STOP     : unsigned (1 downto 0) := "11"
  );
  port (
    clk : in std_logic;
    rstn : inout std_logic;
    tx : out std_logic
  );
end entity;

architecture from_verilog of txstr is

 component uart_tx is
    generic ( BAUDRATE : natural := B9600; -- BAUDRATE = 9600
              N        : integer := 17 -- Number of bits needed for storing the baudrate divisor = $clog2(BAUDRATE)
     );
    port (
      clk : in std_logic;
      data : in unsigned(7 downto 0);
      ready : out std_logic;
      rstn : in std_logic;
      start : in std_logic;
      tx : out std_logic
    );
  end component;

  -- Connecting wires 
  -- It only counts when the cena control signal is enabled
  signal cena : std_logic;  -- Declared at txstr.v:43
  signal char_count : unsigned(2 downto 0);  -- Declared at txstr.v:42
 
  signal data : unsigned(7 downto 0);  -- Declared at txstr.v:27

  signal ready : std_logic;  -- Declared at txstr.v:25
  signal start : std_logic := '0';  -- Declared at txstr.v:26
 
  signal state : unsigned(1 downto 0);  -- Declared at txstr.v:77
  signal next_state : unsigned(1 downto 0);  -- Declared at txstr.v:78
   
  signal tx_Readable : std_logic := '0';  -- Needed to connect outputs
 
begin
  tx <= tx_Readable;
  rstn <= '0';
 
  -- Serial Unit instantation
  -- Generated from instantiation at txstr.v:33
  TX0: uart_tx
    port map (
      clk => clk,
      data => data,
      ready => ready,
      rstn => rstn,
      start => start,
      tx => tx_Readable
    );
   
  -- Characters counter
  -- Counter enable
  -- Generated from always process in txstr (txstr.v:62)
  process is
  begin
    wait until rising_edge(clk);
    if (not rstn) = '1' then
      char_count <= "000";
    else
      if cena = '1' then
        char_count <= char_count + 1;
      end if;
    end if;
  end process;   

  -- Multiplexer with the 8-character string to transmit
  -- Generated from always process in txstr (txstr.v:46)
  process (char_count) is
  begin
    case char_count is
      when "000" =>
        data(0 downto 0) <= to_unsigned(character'pos('H') , 1);
      when "001" =>
        data(1 downto 1) <= to_unsigned(character'pos('e') , 1);
      when "010" =>
        data(2 downto 2) <= to_unsigned(character'pos('l') , 1);
      when "011" =>
        data(3 downto 3) <= to_unsigned(character'pos('l') , 1);
      when "100" =>
        data(4 downto 4) <= to_unsigned(character'pos('o') , 1);
      when "101" =>
        data(5 downto 5) <= to_unsigned(character'pos('!') , 1);
      when "110" =>
        data(6 downto 6) <= to_unsigned(character'pos('.') , 1);
      when "111" =>
        data(7 downto 7) <= to_unsigned(character'pos('.') , 1);
      when others =>
        NULL;
    end case;
  end process;
   
 
 
  -- Transition between states
  -- Generated from always process in txstr (txstr.v:81)
  process (clk) is
  begin
    if rising_edge(clk) then
      if (not rstn) = '1' then
        state <= INI;
      else
        state <= next_state;
      end if;
    end if;
  end process;
 
  -- Control signal generation and next states
  -- Generated from always process in txstr (txstr.v:89)
  process (state, ready, char_count) is
  begin
    next_state <= state;
    start <= '0';
    cena <= '0';
   
    case state is
      when INI =>
        start <= '1';
        next_state <= TXCAR;
      when TXCAR =>
        if ready = '1' then
          next_state <= NEXTCAR;
        end if;
      when NEXTCAR =>
        cena <= '1';
        if (char_count = 7) then
          next_state <= STOP;
        else
          next_state <= INI;
        end if;
      when others =>
        null;
    end case;
  end process;
 
end architecture;


5) plik constraints txtstr_UCF.ucf jest w obu przypadkach identyczny:

Kod programu: Zaznacz cały

NET "clk"       LOC = P129;
NET "clk"       PERIOD = 12MHz;

NET "rstn" PULLUP;
NET "rstn"  LOC = "P75"; //SW 5

NET "tx"  LOC = "P31" | IOSTANDARD = LVCMOS33; //Pin 1


W zalącznikach projekt oryginalny ISE w Verilogu i przetłumaczony w VHDL.
Będę się starał ustalić, gdzie tkwi błąd, ale jeśli ktoś mógłby dać mi jakieś wskazówki - będę bardzo wdzięczny :mrgreen:

A, sorry za niespójne tłumaczenie stanów w poszczególnych entity :oops:

Pozdrawiam

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UART_SEND_VHDL.zip
Projekt ISE UART - VHDL
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UART_SEND.zip
Projekt ISE UART - Verilog
Pobierz Plik ściągnięto 6 raz(y) 20.24 MB


Anioły to też demony - lepiej ich nie wkurzaj
Ostatnio zmieniony przez FlyingDutch 14-01-2018, 13:31, w całości zmieniany 10 razy  
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Elvis 



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Wysłany: 14-01-2018, 16:56   

Nie wiem, czy to najlepszy pomysł żeby brać gotowe programy i je konwertować automatem... Nie lepiej przepisać przykład z książki - po pierwsze jest w VHDL-u, po drugie autor udostępnia opis, więc łatwiej zrozumieć o co chodzi. Transmisja przez port szeregowy jest opisana np. tutaj: https://helion.pl/ksiazki/uklady-fpga-w-przykladach-piotr-zbysinski-majewski-jacek,a_013s.htm#format/d
Automat mocno popsuł program. Po pierwsze linia rstn jest typu inout - zmiana na in sprawia, że dostajemy coś co się syntetyzuje poprawnie. Niestety nadal nie działa - wysyła dane, ale nie jest to oczekiwany efekt. Więc program należałoby teraz przeanalizować i poprawić.
Moim zdaniem to bez sensu - w książce to wszystko już jest - poza tym kod jest dużo prostszy i krótszy.

Efekt działania:

Ostatnio zmieniony przez Elvis 14-01-2018, 16:59, w całości zmieniany 1 raz  
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FlyingDutch 




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Wysłany: 14-01-2018, 18:10   

Elvis napisał/a:
Nie wiem, czy to najlepszy pomysł żeby brać gotowe programy i je konwertować automatem... Nie lepiej przepisać przykład z książki - po pierwsze jest w VHDL-u, po drugie autor udostępnia opis, więc łatwiej zrozumieć o co chodzi. Transmisja przez port szeregowy jest opisana np. tutaj: https://helion.pl/ksiazki/uklady-fpga-w-przykladach-piotr-zbysinski-majewski-jacek,a_013s.htm#format/d
Automat mocno popsuł program. Po pierwsze linia rstn jest typu inout - zmiana na in sprawia, że dostajemy coś co się syntetyzuje poprawnie. Niestety nadal nie działa - wysyła dane, ale nie jest to oczekiwany efekt. Więc program należałoby teraz przeanalizować i poprawić.
Moim zdaniem to bez sensu - w książce to wszystko już jest - poza tym kod jest dużo prostszy i krótszy.


Cześć Elvis,

to była taka pierwsza przymiarka do tematu (pojawia się on dość często). Jeśli stwierdzę, że się nie sprawdza to z rezygnuję z tego podejścia. Przykładów kodu do obsługi UART w sieci jest sporo, jednak ten był fajnie napisany (może to subiektywne odczucie). Dzięki za uwagę z sygnałem rstn - sprawdzę to.

Pozdrawiam


Anioły to też demony - lepiej ich nie wkurzaj
Postaw piwo autorowi tego posta
 
 
JTyburski 



Posty: 66
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Skąd: Warszawa
Programuję w:
VHDL, Verilog
Wysłany: 14-01-2018, 21:00   

Jak już zostało wspomniane przy temacie z translacją - po prostu jemu chodzi o czas, żeby spore porcje kodów bezboleśnie od razu konwertować (też zwracałem na to uwagę, że te translację to są wyjątkowo nieoptymalnie robione) ^^

Warto przeczytać » Raspberry Pi 3 - instalacja systemu w 6 krokach + konkurs


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FlyingDutch 




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Wysłany: 15-01-2018, 12:40   Błędy ISE 64-bit po update Windows 10

Cześć,

wiele wskazuje na to, że podczas wczytania łatki bezpieczeństawa dla Windows10 (64-bit) (błędy CPU - Spectrum) uległo uszkodzeniu środowisko ISE 14.7

Używałem, do syntezy wersji 64-bitowej ISE 14.7 (bo była szybsza), myślałem, że błędna translacja z Verilogu do VHDL jest przyczyną. Sprawdziłem na działającyh projektach (w których nic nie zmieniałem) i też synteza jest błędna. Po wczytaniu krytycznej poprawki do Windows10 Vivado przestało się nawet uruchamiać. Synteza w wersji 32-bitowej zaczyna się a potem trwa w nieskończoność.

Pozdrawiam

Update: Przeinstalowałem ISE (Win10), ale synteza w wersji 64-bitowej w ogóle nie działa - zawsze kończy się porażka bez podania jakichś konkretnych błędów.

Czas syntezy w wersji 32-bitowej rośnie asymptotycznie do nieskończoności :evil:

Niech się Microsoft wypcha ze swoim Windowsem 10.

Pozdrawiam


Anioły to też demony - lepiej ich nie wkurzaj
Ostatnio zmieniony przez FlyingDutch 15-01-2018, 15:13, w całości zmieniany 1 raz  
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Elvis 



Posty: 1729
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C, asm
Wysłany: 19-01-2018, 22:11   

W końcu udało mi się pobawić trochę FPGA - udało mi się doprowadzić kod do działającego stanu. Nie wiem, czy nadal jest potrzebny, ale na wszelki wypadek wkleję:
baudgen_tx.vhd
Kod programu: Zaznacz cały
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use Work.baudrates.all;

entity baudgen_tx is
  generic ( BAUDRATE : natural := B9600; -- BAUDRATE = 9600
            N        : integer := 17 -- Number of bits needed for storing the baudrate divisor = $clog2(BAUDRATE)
  );
   port (
    clk : in std_logic;
    clk_ena : in std_logic;
    clk_out : out std_logic;
    rstn : in std_logic
  );
end entity;

architecture from_verilog of baudgen_tx is
    signal divcounter : STD_LOGIC_VECTOR(N-1 downto 0);   
begin
 
  process (clk) is
  begin
    if rising_edge(clk) then
      if rstn = '0' then
        divcounter <=  (others => '0');
      else
        if clk_ena = '1' then
           if (divcounter = std_logic_vector(to_unsigned(BAUDRATE - 1, divcounter'length))) then
              divcounter <= (others => '0');
           else
             divcounter <= std_logic_vector(unsigned(divcounter) + 1 );
           end if;   
        else
          divcounter <= std_logic_vector(to_unsigned(BAUDRATE - 1, divcounter'length));
        end if;
      end if;
    end if;
  end process;
 
clk_out <= clk_ena when (divcounter = std_logic_vector(to_unsigned(0, divcounter'length))) else '0';
   
end architecture;


uart_tx.vhd
Kod programu: Zaznacz cały
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use Work.baudrates.all;

--- Serial transmitter unit module
--- TX output is not registered
entity uart_tx is
  generic ( BAUDRATE : natural := B9600; -- BAUDRATE = 9600
            N        : integer := 17 -- Number of bits needed for storing the baudrate divisor = $clog2(BAUDRATE)
  );
  port (
    clk : in std_logic;
    data : in unsigned(7 downto 0);
    ready : out std_logic;
    rstn : in std_logic;
    start : in std_logic;
    tx : out std_logic
  );
end entity;

architecture from_verilog of uart_tx is

  component baudgen_tx is
    generic ( BAUDRATE : natural := B9600; -- BAUDRATE = 9600
            N        : integer := 17 -- Number of bits needed for storing the baudrate divisor = $clog2(BAUDRATE)
    );
    port (
      clk : in std_logic;
      clk_ena : in std_logic;
      clk_out : out std_logic;
      rstn : in std_logic
    );
  end component;

-- Transmission clock
signal clk_baud : std_logic;
-- Bitcounter
signal bitc : unsigned(3 downto 0);
-- Registered data
signal data_r : unsigned(7 downto 0);
--------- control signals
signal load : std_logic;  -- Load the shifter register / reset
signal baud_en : std_logic; -- Enable the baud generator

-- localparam IDLE  = 0;  //-- Idle state
-- localparam START = 1;  //-- Start transmission
-- localparam TRANS = 2;  //-- Transmitting data

-- fsm states - original
--signal IDLE : integer range 0 to 2 := 0; -- Idle state
--signal START : integer range 0 to 2 := 1; -- Start transmission
--signal TRANS : integer range 0 to 2 := 2; -- Transmitting data

-- Registers for storing the states
type STATE_T is (IDLE, STARTS, TRANS);
signal state, next_state: STATE_T;

signal ready_Reg : std_logic ;
signal tx_Reg : std_logic ;

-- 1 bit start + 8 bits datos + 1 bit stop
-- Shifter register. It stored the frame to transmit:
-- 1 start bit + 8 data bits + 1 stop bit
signal shifter : unsigned(9 downto 0);  -- Declared at uart_tx.v:69
--signal shifter : std_logic_vector(9 downto 0) := (others=>'0');
 
begin
  ready <= ready_Reg;
  tx <= tx_Reg;
 
  -- Generated from instantiation at uart_tx.v:108
  BAUD0: baudgen_tx
    port map (
      clk => clk,
      clk_ena => baud_en,
      clk_out => clk_baud,
      rstn => rstn
    );
 
  -- Register the input data
  process (clk) is
  begin
    if rising_edge(clk) then
      if start = '1' and state = IDLE then
        data_r <= data;
      end if;
    end if;
  end process;
 
  -- When the control signal load is 1, the frame is loaded
  -- when load = 0, the frame is shifted right to send 1 bit,
  --   at the baudrate determined by clk_baud
  --  1s are introduced by the left
  process (clk) is
  begin
    if rising_edge(clk) then
      if rstn = '0' then
        shifter <= "1111111111";
      else
        if load = '1' then
          shifter <= data_r & "01";
        elsif clk_baud = '1' then
          shifter <= '1' & shifter(9 downto 1);
        end if;
      end if;
    end if;
  end process;
   
  -- Sent bit counter
  -- When load (=1) the counter is reset
  -- When load = 0, the sent bits are counted (with the raising edge of clk_baud)
  process (clk) is
  begin
    if rising_edge(clk) then
      if rstn = '0' then
        bitc <= X"0";
      else
        if load = '1' then
          bitc <= X"0";
        elsif clk_baud = '1' then
            bitc <= bitc + X"1";
        end if;
      end if;
    end if;
  end process;
 
  -- Generated from always process in uart_tx (uart_tx.v:103)
  process (clk) is
  begin
    if rising_edge(clk) then
      tx_Reg <= shifter(0);
    end if;
  end process;
     
  ------------------------------
  -- CONTROLLER
  ------------------------------
 
  -- Transition between states
  process (clk) is
  begin
    if rising_edge(clk) then
      if rstn = '0' then
        state <= IDLE;
      else
        state <= next_state;
      end if;
    end if;
  end process;
 
  -- Generated from always process in uart_tx (uart_tx.v:128)
  -- Control signal generation and next states
  process (state, start, bitc) is
  begin
    -- Default values
    next_state <= state; -- Stay in the same state by default
    load <= '0';
    baud_en <= '0';

    case state is
       -- Idle state
      -- Remain in this state until start is 1
      when IDLE =>
        ready_Reg <= '1';
        if (start = '1') then
          next_state <= STARTS;
        end if;
        -- 1 cycle long
      -- turn on the baudrate generator and the load the shift register
      when STARTS =>
        load <= '1';
        baud_en <= '1';
        ready_Reg <= '0';
        next_state <= TRANS;
        -- Stay here until all the bits have been sent
      when TRANS =>
        baud_en <= '1';
        ready_Reg <= '0';
        if bitc = "1011" then
          next_state <= IDLE;
        end if;
      when others =>
        ready_Reg <= '0';
    end case;
  end process;
 
end architecture;


txstr.vhd
Kod programu: Zaznacz cały
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use Work.baudrates.all;

-- Top entity
-- Generated from Verilog module txstr (txstr.v:16)
--   BAUDRATE = 104
--   INI = 0
--   NEXTCAR = 2
--   STOP = 3
--   TXCAR = 1
entity txstr is
  generic ( BAUDRATE : natural := B9600; -- BAUDRATE = 9600
                INI      : unsigned (1 downto 0) := "00";
                TXCAR    : unsigned (1 downto 0) := "01";
                NEXTCAR  : unsigned (1 downto 0) := "10";
                STOP     : unsigned (1 downto 0) := "11"
  );
  port (
    clk : in std_logic;
    rstn : in std_logic;
    tx : out std_logic
  );
end entity;

architecture from_verilog of txstr is

 component uart_tx is
    generic ( BAUDRATE : natural := B9600; -- BAUDRATE = 9600
              N        : integer := 17 -- Number of bits needed for storing the baudrate divisor = $clog2(BAUDRATE)
     );
    port (
      clk : in std_logic;
      data : in unsigned(7 downto 0);
      ready : out std_logic;
      rstn : in std_logic;
      start : in std_logic;
      tx : out std_logic
    );
  end component;

  -- Connecting wires
  -- It only counts when the cena control signal is enabled
  signal cena : std_logic := '0';
  signal char_count : unsigned(2 downto 0) := "000";
 
  signal data : unsigned(7 downto 0); 

  signal ready : std_logic := '0'; 
  signal start : std_logic := '0';
 
  signal state : unsigned(1 downto 0); 
  signal next_state : unsigned(1 downto 0);
   
  signal tx_Readable : std_logic := '0';  -- Needed to connect outputs
 
begin
  tx <= tx_Readable;
 
  -- Serial Unit instantation
  TX0: uart_tx
    port map (
      clk => clk,
      data => data,
      ready => ready,
      rstn => rstn,
      start => start,
      tx => tx_Readable
    );
   
  -- Characters counter
  -- Counter enable
  process (clk) is
  begin
    if rising_edge(clk) then
        if rstn = '0' then
            char_count <= (others => '0');
        elsif cena = '1' then
            char_count <= char_count + 1;
      end if;
    end if;
  end process;   

  -- Multiplexer with the 8-character string to transmit
  process (clk) is
  begin
    case char_count is
      when "000" =>
        data <= to_unsigned(character'pos('H'), data'length);
      when "001" =>
        data <= to_unsigned(character'pos('e'), data'length);
      when "010" =>
        data <= to_unsigned(character'pos('l'), data'length);
      when "011" =>
        data <= to_unsigned(character'pos('l'), data'length);
      when "100" =>
        data <= to_unsigned(character'pos('o'), data'length);
      when "101" =>
        data <= to_unsigned(character'pos('!'), data'length);
      when "110" =>
        data <= to_unsigned(character'pos('.'), data'length);
      when "111" =>
        data <= to_unsigned(character'pos('.'), data'length);
      when others =>
        NULL;
    end case;
  end process;
   
  -- Transition between states
  process (clk) is
  begin
    if rising_edge(clk) then
      if rstn = '0' then
        state <= INI;
      else
        state <= next_state;
      end if;
    end if;
  end process;
 
  -- Control signal generation and next states
  process (state, char_count, ready) is
  begin
    next_state <= state;
    start <= '0';
    cena <= '0';
   
    case state is
      when INI =>
        start <= '1';
        next_state <= TXCAR;
      when TXCAR =>
        if ready = '1' then
          next_state <= NEXTCAR;
        end if;
      when NEXTCAR =>
        cena <= '1';
        if char_count = 7 then
          next_state <= STOP;
        else
          next_state <= INI;
        end if;
      when others =>
        null;
    end case;
  end process;
 
end architecture;



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FlyingDutch 




Posty: 287
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Skąd: Bydgoszcz
Programuję w:
C++,Python
Wysłany: 21-01-2018, 12:44   

Elvis napisał/a:
W końcu udało mi się pobawić trochę FPGA - udało mi się doprowadzić kod do działającego stanu. Nie wiem, czy nadal jest potrzebny, ale na wszelki wypadek wkleję:
...


Cześć Elvis,

przepraszam za odpowiedź z opóźnieniem, ale dopiero co wróciłem z wyjazdu służbowego :cry:

Jestem Ci bardzo wdzięczny za poprawienie kodu UART. Chciałem to dokończyć, ale miałem sporo innych bardziej priorytetowych prac (no i ISE mi się rozjechało).

Elvis naprawdę duży szacun za tą poprawkę :-D

Pozdrawiam


Anioły to też demony - lepiej ich nie wkurzaj
Ostatnio zmieniony przez FlyingDutch 21-01-2018, 16:56, w całości zmieniany 1 raz  
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