library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity sevseg is
Port ( clk : in STD_LOGIC;
led_seg : out STD_LOGIC_VECTOR (6 downto 0);
led_out : out STD_LOGIC_vector (7 downto 0);
dp : out std_logic
);
end sevseg;
architecture Behavioral of sevseg is
signal digit : std_logic_vector (3 downto 0);
signal counter :std_logic_vector (25 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if counter = 0 then
digit <= digit +1;
end if;
counter <= counter +1;
end if;
end process;
with digit
select led_seg <=
not "1111110" when "0000",
not "0110000" when "0001",
not "1101101" when "0010",
not "1111001" when "0011",
not "0110011" when "0100",
not "1011011" when "0101",
not "1011111" when "0110",
not "1110000" when "0111",
not "1111111" when "1000",
not "1111011" when "1001",
not "1110111" when "1010",
not "0011111" when "1011",
not "1001110" when "1100",
not "0111101" when "1101",
not "1001111" when "1110",
not "1000111" when others;
led_out <= "01111111";
dp <= '1';
end Behavioral;
ok, dzieki.
U mnie to zadzialalo tak.