FlyingDutch Napisano Maj 13, 2018 Udostępnij Napisano Maj 13, 2018 Witam wszystkich, chciałem napisać "test bench" (kod symulacji) dla głównego entity (projekt) dla "fpu_top" z projektu jednostki FPU (opisywanego w wcześniejszym poście): https://www.forbot.pl/forum/topics51/ip-core-fpu_double-problem-z-dlugosciami-magistral-3-x-64-bity-vt15487.htm W "ISE" mieliśmy fajnego "wizard'a", który na podstawie kodu w VHDL danego entity generował "test baench'a" (z procesem stymulacji portów wejściowych), niestety w Vivado nic takiego nie ma. Rozwiązaniem może być generator "test bench" on-line. podaję link: http://vhdl.lapinoo.net/testbench/tb.php Dla przykładu wkleiłem kod głównego entity jednostki FPU Double: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; library work; use work.comppack.all; use work.fpupack.all; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fpu_top is PORT( in8bitA : in STD_LOGIC_VECTOR (7 downto 0); selA : in STD_LOGIC_VECTOR (2 downto 0); --Adress of 8-bit input (4 parts) strobeA : in STD_LOGIC; -- Active rising edge resetLA : in STD_LOGIC; -- Active LOW ---- in8bitB : in STD_LOGIC_VECTOR (7 downto 0); selB : in STD_LOGIC_VECTOR (2 downto 0); --Adress of 8-bit input (4 parts) strobeB : in STD_LOGIC; -- Active rising edge resetLB : in STD_LOGIC; -- Active LOW ---- sysclk, prst, penable : IN std_logic; prmode : IN std_logic_vector (1 DOWNTO 0); pfpu_op : IN std_logic_vector (2 DOWNTO 0); pout_fp: OUT std_logic_vector (7 DOWNTO 0); -- 8 bit out after Multiplexer pready, punderflow, poverflow, pinexact : OUT std_logic; pexception, pinvalid : OUT std_logic; -- selMux : in STD_LOGIC_VECTOR (2 downto 0); --Adress of 8-bit input (4 parts) strobeMux : in STD_LOGIC; -- Active rising edge resetLMux : in STD_LOGIC -- Active LOW ); end fpu_top; architecture Behavioral of fpu_top is component clk_pll is port ( reset : in STD_LOGIC; sys_clock : in STD_LOGIC; clk_out1_0 : out STD_LOGIC; locked_0 : out STD_LOGIC ); end component; component SyncToClock is generic ( NUM_SYNC_STAGES_G : natural := 2 ); port ( clk_i : in std_logic; -- Clock for the domain being entered. unsynced_i : in std_logic; -- Signal that is entering domain. synced_o : out std_logic -- Signal sync'ed to clock domain ); end component; component Demux8To64 is Port ( in8bit : in STD_LOGIC_VECTOR (7 downto 0); sel : in STD_LOGIC_VECTOR (2 downto 0); --Adress of 16-bit input (4 parts) out64bit : out STD_LOGIC_VECTOR (63 downto 0); strobe : in STD_LOGIC; -- Active rising edge resetL : in STD_LOGIC; -- Active LOW CLK : in STD_LOGIC -- clock ); end component; component fpu_double IS PORT( clk, rst, enable : IN std_logic; rmode : IN std_logic_vector (1 DOWNTO 0); fpu_op : IN std_logic_vector (2 DOWNTO 0); opa, opb : IN std_logic_vector (63 DOWNTO 0); out_fp: OUT std_logic_vector (63 DOWNTO 0); ready, underflow, overflow, inexact : OUT std_logic; exception, invalid : OUT std_logic ); end component; component Mux64To16 is Port ( in64bit : in STD_LOGIC_VECTOR (63 downto 0); sel : in STD_LOGIC_VECTOR (2 downto 0); --Adress of 16-bit input (4 parts) out8bit : out STD_LOGIC_VECTOR (7 downto 0); strobe : in STD_LOGIC; -- Active rising edge resetL : in STD_LOGIC; -- Active LOW CLK : in STD_LOGIC -- clock ); end component; signal outDemuxA : STD_LOGIC_VECTOR (63 downto 0); signal outDemuxB : STD_LOGIC_VECTOR (63 downto 0); signal fpuOut64bit : STD_LOGIC_VECTOR (63 downto 0); signal strobeASync : STD_LOGIC; signal strobeBSync : STD_LOGIC; signal strobeMuxSync : STD_LOGIC; signal clk100MHz1 : STD_LOGIC; signal clkLocked : STD_LOGIC; begin clk_pll_i : component clk_pll port map ( clk_out1_0 => clk100MHz1, locked_0 => clkLocked, reset => prst, sys_clock => sysclk ); SyncCLK1 : SyncToClock port map (clk100MHz1, strobeA, strobeASync); SyncCLK2 : SyncToClock port map (clk100MHz1, strobeB, strobeBSync); SyncCLK3 : SyncToClock port map (clk100MHz1, strobeMux, strobeMuxSync); DmuxA : Demux8To64 port map (in8bitA, selA, outDemuxA, strobeASync, resetLA, clk100MHz1); DmuxB : Demux8To64 port map (in8bitB, selB, outDemuxB, strobeBSync, resetLB, clk100MHz1); FPUD : fpu_double port map (clk100MHz1, prst, penable, prmode, pfpu_op, outDemuxA, outDemuxB, fpuOut64bit, pready, punderflow, poverflow, pinexact, pexception, pinvalid ); MuxOut: Mux64To16 port map ( fpuOut64bit, selMux, pout_fp, strobeMuxSync, resetLMux, clk100MHz1 ); end Behavioral; Oto kod test bench'a wygenerowany przez ten generator on-line: -- Testbench automatically generated online -- at http://vhdl.lapinoo.net -- Generation date : 13.5.2018 08:42:33 GMT library ieee; use ieee.std_logic_1164.all; entity tb_fpu_top is end tb_fpu_top; architecture tb of tb_fpu_top is component fpu_top port (in8bitA : in std_logic_vector (7 downto 0); selA : in std_logic_vector (2 downto 0); strobeA : in std_logic; resetLA : in std_logic; in8bitB : in std_logic_vector (7 downto 0); selB : in std_logic_vector (2 downto 0); strobeB : in std_logic; resetLB : in std_logic; sysclk : in std_logic; prst : in std_logic; penable : in std_logic; prmode : in std_logic_vector (1 downto 0); pfpu_op : in std_logic_vector (2 downto 0); pout_fp : out std_logic_vector (7 downto 0); pready : out std_logic; punderflow : out std_logic; poverflow : out std_logic; pinexact : out std_logic; pexception : out std_logic; pinvalid : out std_logic; selMux : in std_logic_vector (2 downto 0); strobeMux : in std_logic; resetLMux : in std_logic); end component; signal in8bitA : std_logic_vector (7 downto 0); signal selA : std_logic_vector (2 downto 0); signal strobeA : std_logic; signal resetLA : std_logic; signal in8bitB : std_logic_vector (7 downto 0); signal selB : std_logic_vector (2 downto 0); signal strobeB : std_logic; signal resetLB : std_logic; signal sysclk : std_logic; signal prst : std_logic; signal penable : std_logic; signal prmode : std_logic_vector (1 downto 0); signal pfpu_op : std_logic_vector (2 downto 0); signal pout_fp : std_logic_vector (7 downto 0); signal pready : std_logic; signal punderflow : std_logic; signal poverflow : std_logic; signal pinexact : std_logic; signal pexception : std_logic; signal pinvalid : std_logic; signal selMux : std_logic_vector (2 downto 0); signal strobeMux : std_logic; signal resetLMux : std_logic; constant TbPeriod : time := 1000 ns; -- EDIT Put right period here signal TbClock : std_logic := '0'; signal TbSimEnded : std_logic := '0'; begin dut : fpu_top port map (in8bitA => in8bitA, selA => selA, strobeA => strobeA, resetLA => resetLA, in8bitB => in8bitB, selB => selB, strobeB => strobeB, resetLB => resetLB, sysclk => sysclk, prst => prst, penable => penable, prmode => prmode, pfpu_op => pfpu_op, pout_fp => pout_fp, pready => pready, punderflow => punderflow, poverflow => poverflow, pinexact => pinexact, pexception => pexception, pinvalid => pinvalid, selMux => selMux, strobeMux => strobeMux, resetLMux => resetLMux); -- Clock generation TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0'; -- EDIT: Check that sysclk is really your main clock signal sysclk <= TbClock; stimuli : process begin -- EDIT Adapt initialization as needed in8bitA <= (others => '0'); selA <= (others => '0'); strobeA <= '0'; in8bitB <= (others => '0'); selB <= (others => '0'); strobeB <= '0'; resetLB <= '0'; prst <= '0'; penable <= '0'; prmode <= (others => '0'); pfpu_op <= (others => '0'); selMux <= (others => '0'); strobeMux <= '0'; resetLMux <= '0'; -- Reset generation -- EDIT: Check that resetLA is really your reset signal resetLA <= '1'; wait for 100 ns; resetLA <= '0'; wait for 100 ns; -- EDIT Add stimuli here wait for 100 * TbPeriod; -- Stop the clock and hence terminate the simulation TbSimEnded <= '1'; wait; end process; end tb; -- Configuration block below is required by some simulators. Usually no need to edit. configuration cfg_tb_fpu_top of tb_fpu_top is for tb end for; end cfg_tb_fpu_top; Jak widać został on wygenerowany całkiem poprawnie. Pozdrawiam Cytuj Link do komentarza Share on other sites More sharing options...
JTyburski Czerwiec 20, 2018 Udostępnij Czerwiec 20, 2018 Testbench to bez względu na środowisko i firmę jest dokładnie taki sam (ot wstawić komponent do kodu i tylko napisać prosty kod do symulacji) - i tyle ^^ Cytuj Link do komentarza Share on other sites More sharing options...
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